1. Field of the Invention
The present invention relates in general to calculation of an absolute value of a difference between two integral numbers, and more particularly to 8-bit absolute value calculation method and circuit for obtaining the difference between the two integral numbers using a conditional subtracter and obtaining the absolute value directly from the obtained difference, resulting in improvement in a calculation speed, so that they can be applied to video and audio compression systems requiring a high-speed absolute value calculation operation.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional absolute value calculation circuit. As shown in this drawing, the conventional absolute value calculation circuit comprises a subtracter 10.1 for taking a complement of one of two input integral numbers A and B and adding the resultant value to the other integral number to obtain a difference between the two integral numbers A and B, an exclusive OR gate 102 for exclusive-ORing an output S of the subtracter 101 to take a one's complement thereof, and an adder 103 for adding "1" to an output of the exclusive OR gate 102 to obtain an absolute value of the difference between the two integral numbers A and B.
The subtracter 101 includes, as shown in FIG. 2, an exclusive OR gate 104 for exclusive-ORing the input integral number B to take a two's complement thereof, and an adder 105 for adding the input integral number A to an output of the exclusive OR gate 104 to obtain the difference S between the two integral numbers A and B.
The operation of the conventional absolute value calculation circuit with the above-mentioned construction will hereinafter be described.
In the case where the absolute value of the difference A-B between the two integral numbers A and B is to be obtained, the two's complement of the integral number B is taken and then added to the integral number A. Then, it is discriminated whether a most significant bit of the added value S is "1". If the most significant bit of the added value S is "1" the two's complement of the added value S is taken because the added value S is a negative (-) value. On the contrary, if the most significant bit of the added value S is "0", the added value S is directly used because it is a positive (+) value.
In the case where the above-mentioned method is to be performed by the circuit, when the two integral numbers A[0:7] and B[0:7] are inputted to the subtracter 101, the one's complement of the integral number B is taken by the exclusive OR gate 104 and then added to "1", resulting in the two's complement of the integral number B being taken. Then, the adder 105 adds the input integral number A to the two's complement of the integral number B. As a result, the difference (S=A-B) between the two integral numbers A and B is obtained by the adder 105.
The adder 105 is an 8-bit ripple carry adder, as shown in FIG. 3, which consists of 8 1-bit adders. In calculating 8-bit data, an output carry of a lower-order bit is transferred to an input carry of a higher-order bit up to a most significant bit. In this manner, the difference (S=A-B) between the two integral numbers A and B is obtained by the adder 105.
If the difference S between the two integral numbers A and B is the negative (-) value, the one's complement thereof is taken by the exclusive OR gate 102 and then added to "1" by the adder 103. As a result, the absolute value of the difference between the two integral numbers A and B is obtained by the adder 103.
For example, provided that A=2 and B=4, A-B=-2 and the absolute value thereof is "2". In this case, the integral numbers A and B can be expressed in binary 8-bit data form as follows:
A="00000010" PA1 B="00000100" PA1 /(A-B).sub.1 =00000001
The one's complement (/B.sub.1 =11111011) of the integral number B is taken by the exclusive OR gate 104 and then added to "1", resulting in the two's complement (/B.sub.2 =11111100) of the integral number B being taken. Namely, /B.sub.2 32 /B.sub.1 +1%.
Adding the integral number A to the two's complement /B.sub.2 of the integral number B, the sum (S=A-B)=A+(-/B.sub.2)=11111110. In this case, because the most significant bit is "1" the difference A-B between the two integral numbers A and B is the negative (-) value.
To obtain the absolute value of the difference A-B between the two integral numbers A and B, the one's complement of the difference A-B is taken by the exclusive OR gate 102 as follows:
Then, the adder 103 adds "1" to the one's complement of the difference A-B to take the two's complement thereof as follows: EQU /(A-B).sub.2 =/(A-B).sub.1 +1=00000010=2
where, "2" is the absolute value.
However, the above-mentioned conventional absolute value calculation circuit has a disadvantage in that the difference S between the two integral numbers A and B is obtained by the 8-bit ripple carry adder requiring a long data calculation time because the carry is transferred from the lower-order bit to the higher-order bit. For this reason, to enhance the low-speed calculation operation of the 8-bit ripple carry adder, a high-speed conditional sum adder has mostly been used to be applicable to a high-speed signal processing system.
Although employing the high-speed conditional sum adder, however, the conventional absolute value calculation circuit has another disadvantage in that the subtraction operation is performed for the absolute value calculation by taking the two's complement of one of the input data, resulting in the increase in the number of the circuit components and in the calculation time. Further, at the final absolute value calculating stage, an inverter or the exclusive OR gate and the adder must be used to take the two's complement of the sum {A+(-B)} of the two integral numbers A and B according to a sign of the most significant bit thereof. This results in the increase in a chip area and in the calculation time.